Digital information is often stored in dynamic random access memory devices (DRAMs). One type of DRAM transfers information synchronously with a clock signal. This type of DRAM is referred to as synchronous DRAM (SDRAM). SDRAMs provide a burst of four data transfers on every burst read access (when programmed for burst length of 4). In case of 64-bit data bus interface system, such a transfer involves 32 bytes of data per SDRAM access. Current PC systems typically use such an arrangement. The L1 and L2 caches of some of the current x86 CPUs are designed to expect 32 bytes of data per main memory access, which matches the data being delivered by the SDRAM. SDRAM devices transfer information once every clock cycle of the clock signal.
Double Data Rate (DDR) memory devices differ from SDRAM devices in that they transfer data on each edge of the clock signal (i.e., twice every clock cycle of the clock signal), thus doubling the peak throughput of the memory device as compared with SDRAM. DDR memory devices thus provide a burst of eight data transfers on every burst read access (when programmed for burst length of 4).
Unfortunately, memory accessing agents that exchange information with memory devices are designed to transfer the information according to a fixed memory access size. For example, microprocessors include L1 and L2 caches that are designed specifically for 32-byte transfer suitable for SDRAM technology or specifically for 64-byte transfer suitable for DDR memory technology. It has been impractical to design microprocessors to support different cache line sizes to support both SDRAM and DDR memory technologies. Additionally, other memory accessing system agents, for example, a peripheral component interconnect (PCI) interface master device, an accelerated graphics port (AGP) graphics master device, etc., could have different cache size requirements.
However, being able to support both SDRAM and DDR memory technologies with a single computer system design would allow systems to be offered at different price points, which would be very desirable. Also, support for both memory technologies would avoid obstacles to upgrading memory within a computer system. Thus, a technique is needed to provide compatibility for both SDRAM and DDR memory devices within a common system.